EN0-001 Online Practice Questions and Answers

A standard performance benchmark is being run on a single core ARM v7-A processor. The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?

A. L1 Caches and branch prediction are disabled

B. The Embedded Trace Macrocell (ETM) is disabled

C. The Memory Management Unit (MMU) is enabled

D. The Snoop Control Unit (SCU) is disabled

According to the AAPCS, which of the following statements is TRUE with regard to preservation of register values by a function?

A. A function must preserve R0-R3 and R12

B. A function must preserve R4-R11 andR13

C. No registers may be corrupted by any function

D. All registers may be corrupted by any function

Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?

A. No, they are completely incompatible

B. Yes, all Cortex-A9 MPCore processors include an integrated GIC

C. Yes, but a dummy second processor has to be included

D. No, a GIC is only compatible with multi-core Cortex-A9 processors

In which of the following scenarios would cache maintenance operations be necessary in an ARMv7 system?

A. Before executing code that uses the NEON instruction set

B. Before handling an interrupt request raised by an external device

C. Before checking the status of a semaphore

D. Before reading cacheable memory that has been written to by an external bus master

How many ARM core registers and PSRs (Program Status Registers) are available to the programmer in User mode on a Cortex-A9?

A. 16

B. 17

C. 18

D. 32

In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?

A. D0..D31 and S0..S31 are separate register banks

B. D0..D31 overlap with S0..S63

C. D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers

D. D0 overlaps with S0, D1 with S1 etc. up to D31 and S31

The ARMv7-A virtual memory management system supports 32-bit (short) and 64-bit (long) page table descriptors. The sizes of a small page in a short descriptor and a small page in a long descriptor are:

A. 1 KB and 4KB respectively

B. 4KB and 4KB respectively

C. 4KB and 16KB respectively

D. 16KB and 16KB respectively

In an operating system environment, most applications are executed in which processor mode?

A. Supervisor

B. IRQ

C. System

D. User

Which of the following is an advantage of the single-step debug technique?

A. It allows a complete trace of real-time program execution to be captured

B. It reduces the number of pins required to connect the debugger to the processor

C. It allows examination of the system state before and after execution of a statement

D. It requires only one change to the program source code

When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?

A. Writes dirty data cache lines to memory

B. Reloads dirty data cache lines from memory

C. Speculatively preloads data into the cache

D. Writes dirty data cache lines to memory and marks those lines as invalid

According to the AAPCS, how many bytes are used to store a C variable of type 'int' in memory?

A. 1 byte

B. 2 bytes

C. 4 bytes

D. 8 bytes

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

A. Cache Size

B. Clock Speed

C. Program size

D. Numbers of instructions executed

Clicking the Start button in a debugger:

A. Begins processor execution.

B. Resets the processors.

C. Erases existing breakpoints.

D. Puts the processor(s) into debug state.

In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)

A. The time spent waiting for I/O operations

B. The time taken to download the program via the debugger

C. The time taken for memory accesses

D. The time taken for the CPU to execute instructions

E. The time taken to compile the source code

F. The time taken to perform instruction tracing

An ARM Cortex-A9 multi-core system has two CPUs, C1 and C2, each with a corresponding data cache. The code running on C1 writes to a memory location M. and C1 updates its data cache, but not main memory. After that, C2 tries to read the contents of memory location M. Which of the following hardware can automatically (without software inteivention) ensure that C2 reads the updated contents of M?

A. Snoop Control Unit

B. Tightly Coupled Memory

C. Level 2 Cache Controller

D. Dynamic Memory Access Controller